Magnus Eventide Page


H949 User and Service Manual

Front sheets

I Front cover
II Warranty Page
III Warranty Registration Form (now slightly out of date)

User Manual

1 Tables of Content, Introduction
2 Control Description, Power On/Off, Line In/Out
3 Input Level Control and Indicator Group, Repeat Control, Feedback Control Group
4 Delay Only Output (MSEC) Switch Group, Pitch Control/Readout Group
5 Function Select Switch Group
6 Pitch Control Group
7 Delay/Random/Flange/Reverse Functions
8 Main Output (MSEC) Delay Set Switch Group, Algorithm Select 1/2
9 Remote Control, Voltage Control of Pitch Ratio
10 Resistive Control of Pitch Ratio, Frequency Control of Pitch Ratio
11 Rear Panel Connectors, Grounding
12 (cont)
13 (cont)
14 (cont)
15 HK940 - Keyboard fpr Eventide Harmonizer Model H910 and H949
16 (cont)

Technical Section

TS D i Tables of Content, Introduction
TS D ii (cont)
T1 Alignment Instructions
T2 (cont)
T3 Service Section, Introduction to Service Section
T4 (in 200 DPI) Power Supply
T5 HA931 basic layout
T6 Audio Processing, Input Processing, Output Processing, Pitch Change Timing and Control Circuitry
T7 Read Fifo Clock Select, Voltage Controlled Oscillator (VCO)
T8 (cont)
T9 Single Side Band Generator - SSB
T10 Voltage Controlled Quadrature Oscillator
T11 Pseudo Random Noise Generator, Tape Capstan Drive, Audio Level Display
T12 HD921 basic layout
T13 Master Oscillator, Program Counter, Timing PROM, Central Processing Unit (CPU)
T14 Micro-Instruction (uINST) PROMs
T15 Conditional Micro-Instructions, Conditional CPU Register Addresses
T16 Status Flags, CPU Data Input, CPU Analog Output
T17 11x16k Dynamic RAM Array, Analog-To-Digital Converter (ADC), Delay Only Output
T18 Fixed Delay Output, First-In First-Out (FIFO) Registers, Main Output DAC
T19 Main Output Reference Voltage
T20 HP941, Input Level, Feedback, Delay Set Switches, Function Select, Algorithm Select
T21 Control Mode Select, Pitch Ratio Readout
S1 Master Block Diagram
S2 Input Audio Processing, Output Audio Processing
S3 Pitch Change Timing & Control, System Timing & Central Processing Unit
S4 (in 200 DPI) HA931 1/6 - Input Audio Processing
S5 HA931 2/6 - Output Audio Processing
S6 HA931 3/6 - Voltage Controlled Oscillator and Read FIFO Clock Select
S7 HA931 4/6 - Single Side Band Generator
S8 HA931 5/6 - Function Select Logic, Audio Level Indicators, Pseudo Random Noise Generator, Capstain Drive and Display Timing Circuitry
S9 HA931 6/6 - Power Supply
S10 HD921 1/7 - Master Oscillator, Program Counters and Analog-To-Digital Converter
S11 (in 200 DPI) HD921 2/7 - Timing and Micro-Instruction Programmable Read-Only-Memories (PROMs)
S12 HD921 3/7 - CPU Status Flags and Conditional uINSTR Logic
S13 HD921 4/7 - 16-bit Central Processing Unit (CPU) and 11x16k Dynamic Random Access Memory Array (RAM)
S14 HD921 5/7 - Data PROM, CPU Analog Out and RAM Address and Timing
S15 HD921 6/7 - FIFO Array and Timing, Main Output DAC
S16 HD921 7/7 - Main Output Reference Voltage and Delay Only DAC
S17 HP941 1/2 - Audio Control and Delay Set
S18 HP941 2/2 - Function Select, Control and Display
S19 (in 200 DPI) dbx Model 303C Type II schematic
S20 Inter-Board Connectors
S21 Ribbon Cable Harnesses
S22 Integrated circuits used in H949 Harmonizer
S23 (cont)
S24 (cont)
S25 (cont)
S26 Last Page - The End

Magnus Danielson <cfmd at bredband dot net>